1. Field of the Invention
The invention relates to a photodiode and more particularly to a silicon photodiode with symmetry layout and deep well bias in CMOS technology.
2. Description of Related Art
Nowadays, Si photodiodes (PDs) fabricated by complementary metal-oxide-semiconductor (CMOS) become popular in the application of optical communication at near-infrared wavelengths (e.g. 850-nm) due to its low cost and possible integration with receivers. However, light penetration depth of Si at 850-nm is larger than 10 μm that results in low responsivity for a surface PD. Moreover, carriers generated from bulk silicon substrate slowly diffuse to be collected and significantly affect the response performance. The resulting bandwidth is limited.
It is possible to improve both responsivity and bandwidth by avalanche diode structure. However, the response time is still limited by the slow diffusion carriers in the substrate. As a result, silicon photodiodes fabricated on silicon-on-insulator (SOI) substrates present the best performance, but the cost and popularity of SOI wafers are two issues.